As a transistor structure for decreasing the power consumption of a semiconductor device, the structure called DTMOS (Dynamic Threshold Voltage MOSFET) is proposed. DTMOS has the transistor structure that the body electrodes of the respective transistors are isolated by using an SOI substrate, and the gate electrode and the body electrode are short-circuited. DTMOS provides a large drive current when the transistor is ON and, when the transistor is OFF, has a threshold voltage relatively higher than when the transistor is ON, whereby the leakage current can be suppressed, and the power consumption can be decreased.
The followings are examples of related: Japanese Laid-open Patent Publication No. 09-074189; Japanese Laid-open Patent Publication No. 11-074522; Japanese Laid-open Patent Publication No. 2002-208696; Japanese Laid-open Patent Publication No. 2004-087671; and Japanese Laid-open Patent Publication No. 2006-502573.
For further speediness and low power consumption of transistors, a structure of semiconductor device which can further decrease the parasitic capacitance, and its manufacturing method are expected.